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Features
* * * *
Single Supply for Read and Write: 2.7V to 5.5V Fast Read Access Time - 70 ns (VCC = 2.7V to 3.6V); 55 ns (VCC = 4.5V to 5.5V) Internal Program Control and Timer Flexible Sector Architecture - One 16K Bytes Boot Sector with Programming Lockout - Two 8K Bytes Parameter Sectors - Eight Main Memory Sectors (One 32K Bytes, Seven 64K Bytes) Fast Erase Cycle Time - 8 Seconds Byte-by-Byte Programming - 10 s/Byte Typical Hardware Data Protection DATA Polling or Toggle Bit for End of Program Detection Low Power Dissipation - 20 mA Active Current - 25 A CMOS Standby Current for VCC = 2.7V to 3.6V - 30 A CMOS Standby Current for VCC = 4.5V to 5.5V Minimum 100,000 Write Cycles
* * * * *
4-megabit (512K x 8) Flash Memory AT49BV040B
*
1. Description
The AT49BV040B is a 2.7V to 5.5V in-system reprogrammable Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers an access time of 70 ns (VCC = 2.7V to 3.6V) and an access time of 55 ns (VCC = 4.5V to 5.5V). The power dissipation over the industrial temperature range with VCC = 2.7V to 3.6V is 72 mW and is 110 mW with VCC = 4.5V to 5.5V. When the device is deselected, the CMOS standby current is less than 30 A. To allow for simple in-system reprogrammability, the AT49BV040B does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV040B is performed by erasing a sector of data and then programming on a byte by byte basis. The byte programming time is a fast 10 s. The end of a program or erase cycle can be optionally detected by the DATA polling or toggle bit feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 100,000 cycles. The device is erased by executing a chip erase or a sector erase command sequence; the device internally controls the erase operations. The memory array of the AT49BV040B is organized into two 8K byte parameter sectors, eight main memory sectors, and one boot sector. The device has the capability to protect the data in the boot sector; this feature is enabled by a command sequence. The 16K-byte boot sector includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
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2. Pin Configurations
Pin Name A0 - A18 CE OE WE I/O0 - I/O7 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs
2.1
32-lead PLCC Top View
A12 A15 A16 A18 VCC WE A17
2.2
32-lead VSOP or 32-lead TSOP Top View - Type 1
I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6
14 15 16 17 18 19 20
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE A10 CE I/O7
A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
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3. Block Diagram
DATA INPUTS/OUTPUTS I/O7 - I/O0 VCC GND OE WE CE 8 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING MAIN MEMORY SECTOR 8 (64K BYTES) MAIN MEMORY SECTOR 7 (64K BYTES) MAIN MEMORY SECTOR 6 (64K BYTES) MAIN MEMORY SECTOR 5 (64K BYTES) MAIN MEMORY SECTOR 4 (64K BYTES) MAIN MEMORY SECTOR 3 (64K BYTES) MAIN MEMORY SECTOR 2 (64K BYTES) MAIN MEMORY SECTOR 1 (32K BYTES) PARAMETER SECTOR 2 (8K BYTES) PARAMETER SECTOR 1 (8K BYTES) BOOT SECTOR (16K BYTES) 7FFFF
CONTROL LOGIC
Y DECODER ADDRESS INPUTS
X DECODER
70000 6FFFF
60000 5FFFF
50000 4FFFF 40000 3FFFF
30000 2FFFF
20000 1FFFF
10000 0FFFF
08000 07FFF
06000 05FFF
04000 03FFF 00000
4. Device Operation
4.1 Read
The AT49BV040B is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
4.2
Command Sequences
When the device is first powered on, it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. 3
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4.3
Erasure
Before a byte can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
4.3.1
Chip Erase If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Sector 1, Parameter Sector 2, Main Memory Sectors 1 - 8, but not the boot sector. If the Boot Sector Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored.
4.3.2
Sector Erase As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter sectors and eight main memory sectors. The 8K-byte parameter sectors and the eight main memory sectors can be independently erased and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
4.4
Byte Programming
Once the memory array is erased, the device is programmed (to a logical "0") on a byte-by-byte basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4-bus cycle operation (see "Command Definition Table" on page 7). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling or toggle bit feature may also be used to indicate the end of a program cycle.
4.5
Boot Sector Programming Lockout
The device has one designated sector that has a programming lockout feature. This feature prevents programming of data in the designated sector once the feature has been enabled. The size of the sector is 16K bytes. This sector, referred to as the boot sector, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot sector's usage as a write protected region is optional to the user. The address range of the boot sector is 00000 to 03FFF. Once the feature is enabled, the data in the boot sector can no longer be erased or programmed. Data in the main memory and parameter sectors can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. See "Command Definition Table" on page 7.
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4.5.1 Boot Sector Lockout Detection A software method is available to determine if programming of the boot sector is locked out. When the device is in the software product identification mode (see Software Product Identification Entry/Exit on page 15) a read from address location 00002H will show if programming the boot sector is locked out. If the data on I/O0 is low, the boot sector can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the sector cannot be programmed. The software product identification code should be used to return to standard operation.
4.6
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
4.7
Data Polling
The AT49BV040B features DATA polling to indicate the end of a program or erase cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the erase operation is completed, a "1" will be read from I/O7. The Data Polling status bit must be used in conjunction with the erase/program status bit as shown in the algorithm in Figure 4-1 on page 6.
4.8
Toggle Bit
In addition to DATA polling, the AT49BV040B provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. The toggle bit status bit should be used in conjunction with the erase/program status bit shown in the algorithm in Figure 4-2 on page 6.
4.9
Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a "1", the device is unable to verify that an erase or a byte program operation has been successfully performed. If a program (Sector Erase) command is issued to the boot sector and the boot sector programming lockout feature is enabled, the boot sector will not be programmed (erased), and the device will go into the read mode. Once the erase/program status bit has been set to a "1", the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a "0" while the erase or program operation is still in progress.
4.10
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV040B in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 5
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Figure 4-1.
Data Polling Algorithm
Figure 4-2.
Toggle Bit Algorithm
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0 Addr = VA
Read I/O7 - I/O0
I/O7 = Data?
YES
Toggle Bit = Toggle? YES NO I/O5 = 1? NO
NO NO I/O5 = 1?
YES Read I/O7 - I/O0 Addr = VA
YES Read I/O7 - I/O0 Twice
YES I/O7 = Data? NO Program/Erase Operation Not Successful, Write Product ID Exit Command
Notes:
Toggle Bit = Toggle?
NO
Program/Erase Operation Successful, Device in Read Mode
Note:
YES Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
1. The system should recheck the toggle bit even if I/O5 = "1" because the toggle bit may stop toggling as I/O5 changes to "1".
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5. Command Definition Table
Command Sequence Read Chip Erase Sector Erase Byte Program Boot Sector Lockout(3) Product ID Entry Product ID Exit Product ID Exit Notes:
(4) (4)
Bus Cycles 1 6 6 4 6 3 3 1
1st Bus Cycle Addr Addr 555 555 555 555 555 555 XXX Data DOUT AA AA AA AA AA AA F0
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
AAA(2) AAA AAA AAA AAA AAA
55 55 55 55 55 55
555 555 555 555 555 555
80 80 A0 80 90 F0
555 555 Addr 555
AA AA DIN AA
AAA AAA
55 55
555 SA
(5)
10 30
AAA
55
555
40
1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows: A11 - A0 (Hex); A11 - A18 (don't care). 2. Since A11 is don't care, AAA can be replaced with 2AA. 3. The 16K byte boot sector has the address range 00000H to 03FFFH. 4. Either one of the Product ID Exit commands can be used. 5. SA = sector addresses: SA = 00000 to 03FFF for BOOT SECTOR SA = 04000 to 05FFF for PARAMETER SECTOR 1 SA = 06000 to 07FFF for PARAMETER SECTOR 2 SA = 08000 to FFFF for MAIN MEMORY ARRAY SECTOR 1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY SECTOR 2 SA = 20000 to 2FFFF for MAIN MEMORY ARRAY SECTOR 3 SA = 30000 to 3FFFF for MAIN MEMORY ARRAY SECTOR 4 SA = 40000 to 4FFFF for MAIN MEMORY ARRAY SECTOR 5 SA = 50000 to 5FFFF for MAIN MEMORY ARRAY SECTOR 6 SA = 60000 to 6FFFF for MAIN MEMORY ARRAY SECTOR 7 SA = 70000 to 7FFFF for MAIN MEMORY ARRAY SECTOR 8
6. Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on A9 with Respect to Ground ...................................-0.6V to +10.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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7. Sector Address Table
Sector Boot Sector Parameter Sector 1 Parameter Sector 2 Main Memory Sector 1 Main Memory Sector 2 Main Memory Sector 3 Main Memory Sector 4 Main Memory Sector 5 Main Memory Sector 6 Main Memory Sector 7 Main Memory Sector 8 Sector Size 16K Bytes 8K Bytes 8K Bytes 32K Bytes 64K Bytes 64K Bytes 64K Bytes 64K Bytes 64K Bytes 64K Bytes 64K Bytes Sector Address Range 00000 - 03FFF 04000 - 05FFF 06000 - 07FFF 08000 - 0FFFF 10000 - 1FFFF 20000 - 2FFFF 30000 - 3FFFF 40000 - 4FFFF 50000 - 5FFFF 60000 - 6FFFF 70000 - 7FFFF
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8. DC and AC Operating Range
AT49BV040B Operating Temperature (Case) VCC Power Supply Ind. -40C - 85C 2.7V - 3.6V or 4.5V to 5.5V
9. Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X X X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X
Ai Ai Ai X
I/O DOUT DIN High Z
Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware
X VIL VIH
High Z
A1 - A18 = VIL, A9 = VH,(3), A0 = VIL VIL VIL VIH A1 - A18 = VIL, A9 = VH,(3), A0 = VIH A0 = VIL, A1 - A18 = VIL A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 9.5V 0.5V.
4. Manufacturer Code: 1FH, Device Code: 13H. Additional Device Code: 10H is read from address 0003H. 5. See details under Software Product Identification Entry/Exit on page 15.
10. DC Characteristics
VCC = 2.7V to 3.6V Symbol ILI ILO ISB1 ICC(1) VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 0.7 VCC 0.45 2.4 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC f = 5 MHz; IOUT = 0 mA 15 15 Min Typ Max 1 1 25 20 0.1 VCC 0.7 VCC 0.45 25 15 Min VCC = 4.5V to 5.5V Typ Max 1 1 30 20 0.1 VCC Units A A A mA V V V V
Note:
1. In the erase mode, ICC is 15 mA.
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11. AC Read Characteristics
2.7V to 3.6V Symbol tACC tCE
(1) (2)
4.5V to 5.5V Min Max 55 55 0 0 0 15 25 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 70 70
tOE
0 0 0
35 25
tDF(3)(4) tOH
12. AC Read Waveforms (1)(2)(3)(4)
ADDRESS CE ADDRESS VALID
OE
tCE tOE t DF tACC tOH
OUTPUT VALID
OUTPUT
HIGH Z
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
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13. Input Test Waveform and Measurement Level
0.7 x VCC AC DRIVING LEVELS 0.1 x VCC AC MEASUREMENT LEVEL VCC/2
tR, tF < 5 ns
14. Output Load Test
VCC 1.8K OUTPUT PIN 1.3K 30 pF
15. Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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16. AC Byte Load Characteristics
2.7V to 3.6V Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 20 0 0 30 20 0 20 Max 4.5V to 5.5V Min 0 20 0 0 20 20 0 20 Max Units ns ns ns ns ns ns ns ns
17. AC Byte Load Waveforms
17.1 WE Controlled
OE tOES ADDRESS CE tAS tCS tWPH tWP tDS DATA IN tDH tAH tCH tOEH
WE
17.2
CE Controlled
OE tOES ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH tOEH
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18. Program Cycle Characteristics
2.7V to 3.6V and 4.5V to 5.5V Symbol tBP tAS tAH tDS tDH tWP tWPH tEC tSEC Note: Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Chip Erase Cycle Time Main Sector Erase Cycle Time 1. 20 ns for VCC = 4.5V to 5.5V. 0 20 20 0 30
(1)
Min
Typ 10
Max 120
Units s ns ns ns ns ns ns
20 8 900
seconds ms
19. Program Cycle Waveforms
A0 - A18
20. Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP
WE
tWPH
tAS
A0 - A18
tAH
555
tDH
AAA 555 555 AAA Note 2
tDS
DATA
AA 55 80 AA 55 Note 3
tEC
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase the address depends on what sector is to be erased. (See note 5 under "Command Definition Table" on page 7.) 3. For chip erase, the data should be 10H. For sector erase, the data should be 30H.
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21. Data Polling Characteristics
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
(2)
Min 10 10
Typ
Max
Units ns ns ns
50 0
ns ns
22. Data Polling Waveforms
WE CE tOEH OE tDH I/O7 A0-A18 An tOE HIGH Z tWR tOEHP
An
An
An
An
23. Toggle Bit Characteristics
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
(2)
Min 10 10
Typ
Max
Units ns ns ns
50 0
ns ns
24. Toggle Bit Waveforms(1)(2)(3)
WE CE tOEH OE tDH I/O6 tOE HIGH Z tWR tOEHP
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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25. Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 90 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
27. Boot Block Lockout Feature Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 40 TO ADDRESS 555
26. Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE(4)
OR
LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE 1 second(2)
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A11 - A0 (Hex). 2. Boot block lockout feature enabled.
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A11 - A0 (Hex). 2. A1 - A18 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. Additional Device Code is read for address 0003H 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 13H. Additional Device Code: 10H.
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28. Ordering Information
28.1 Green Package (Pb/Halide-free)
ICC (mA) Active 20 Ordering Code AT49BV040B-JU AT49BV040B-TU AT49BV040B-VU Package 32J 32T 32V Operation Range Industrial (-40 to 85 C)
Package Type 32J 32T 32V 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC) 32-lead, Thin Small Outline Package (TSOP) 32-lead, Thin Small Outline Package (VSOP)
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29. Packaging Information
29.1 32J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM - - - - - - - - - - - 1.270 TYP
MAX 3.556 2.413 - 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
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29.2
32T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 7.90 0.50 NOM - - 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 32T REV. B
R
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29.3 32V - VSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 13.80 12.30 7.90 0.50 NOM - - 1.00 14.00 12.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 14.20 12.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. 32V REV. B
R
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3499B-FLASH-4/06
30. Revision History
Revision No. Revision A - Sept. 2005 Revision B - April 2006 History * * * * Initial Release Combined the 3V and 5V part into one datasheet (BV). Removed the speed of the part form the ordering information table. Changed the address hold time to 20 ns.
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AT49BV040B
3499B-FLASH-4/06
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3499B-FLASH-4/06

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